1. Field of the Invention
The present invention relates generally to a data transfer device and, more particularly, to a peripheral component interconnect (PCI) host bridge device.
2. Description of the Related Art
In 1995, version 2.1 of the PCI specification replaced version 2.0. This new version introduced new requirements intended to better control bus latency and performance. One of these requirements was directed toward maintaining load data ordering in a PCI bridge relative to direct memory access (DMA) write data. Load data, in this case, is a processor initiated transaction to transfer data from an input/output (I/O) device or memory to the processor's caches or registers. DMA write data is an I/O device initiated transaction to transfer data from the I/O device to (system) memory.
The load data ordering requirement mandates that load data from I/O devices never bypass DMA write data in the PCI bridge. To implement this requirement, PCI bridges that conform to version 2.1 of the PCI specification do not forward load data out until all DMA write data currently in the bridges has been forwarded out.
This requirement, in most instances, enhances the performance of the system. For example, when an I/O device finishes a DMA write data transfer, it indicates so by sending an interrupt request (IRQ) to the processor. (Note that an IRQ can bypass write data in the bridge.) If the processor wants to load the DMA write data for processing, to ensure that all the DMA write data is in memory and thus available to be read, the processor sends a dummy load data request to the I/O device in question. If the dummy load data is received by the processor, it is an indication that all the DMA write data is available to be read (since the load data ordering requirement does not allow load data to bypass DMA write data in the bridge, if the dummy load data is received by the processor, then all the DMA write data must have cleared the bridge and thus available to be read). Hence, the processor knows exactly when to load the DMA write data (i.e., it will not start loading the data before all the data is available nor will it wait too long after the data is available to load the data).
Although the load data ordering requirement may in general enhance performance of some computer systems, in certain situations, it may be a detriment to the system. For instance, some computer systems handle error conditions by placing all devices into an error state. When in this state, except for diagnostic data, the devices will stop transmitting or receiving all data. When the system enters this state, the processor is notified through an IRQ. Once notified, the processor starts running diagnostic code to figure out exactly which one of the devices is the culprit. The processor does so by sending diagnostic load requests to the devices and by analyzing the diagnostic data received from the devices. In this case, if there exists DMA write data in the PCI bridge when the system enters the error state, the DMA write data will not clear the bridge since none of the devices are accepting data. Because of the load data ordering requirement, then, the system may become deadlock (i.e., the processor may be waiting for a load data which is not forthcoming because of the DMA write data in the bridge).
Thus, there is a need in the art for a method of disabling load data ordering in a PCI bridge to allow load data to bypass DMA write data in the event the system is in an error state.